This invention relates to a dynamic random access semiconductor memory device which can decrease access time.
The integration density of a dynamic random access semiconductor memory device (dRAM) is more and more improved with an advance in the microminiaturization technique. That is, the performance of memory cells is improved through the microminiaturization of memory cells and a great improvement has been achieved in the access time of the memory cells. If the gate length of the MOS transistors in a memory is reduced on the order of 0.5 .mu.m in odder to effect that microminiaturization, a voltage which is applied to the memory cell has to be lowered so as to secure the reliability of memory cells. The limit has already been reached for the dRAM to operate at high speed with the use of microminiaturized memory cells.
The conventional dRAM comprised of CMOS's (complementary MOS) transistors will be explained below by referring to the bloc diagram of FIG. 1. In the circuit arrangement shown in FIG. 1, memory cell array 1 is comprised of a matrix array of memory cells. Reference numeral 2 shows a multiplex address signal; 3, an address data buffer; 4, a column address buffer; 5, a row address buffer, 6 and 7 clock generators; 8, a column decoder; 9, a row decoder; 10, a bit line sense amplifier, 11, word lines; 12, bit lines; 13, an output data buffer; 14, a refresh counter; and 15, a substrate bias signal generator. The signal paths are as indicated in FIG. 1. Multiplex address signal 2 contains row and column address signals. The column address signal is responsive to a CAS (column address strobe) signal to allow it to be coupled to column decoder 8 through address data buffer 3 and column address buffer 4. On the other hand, the row address signal is responsive to a RAS (row address strobe signal) to allow it to be coupled to row decoder 9 through address data buffer 3 and row address buffer 5. The output of row decoder 9 selects word line 11 while, on the other hand, the output of column decoder 8 selects bi line 12. Bit line sense amplifier 10 is connected between a bit line pair and an I/O (input/output) line pair to amplify a memory cell output so that it is supplied to an I/O line.
In the conventional dRA,, at a first timing a row address is supplied to row address buffer 5 in response to the RAS signal, so that a word line is selected. At a subsequent timing following the first timing, a column address is supplied to column address buffer 4 in response to the CAS signal, so that a bit line is selected. Further, for a differential amplifier constituting a bit line sense amplifier, bipolar transistors have not been used as driving transistors. As a result, about 30 nsec has been required for the operation in which the data in a memory cell is delivered via a selected bit line to a bit line sense amplifier where determination is made as to whether that data is a "H" or a "L" level, the data is transferred to an I/O line and the transferred data is amplified by an I/O line sense amplifier. Such a long time has offered a bar to reading the dRAM data at high speed.